EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 592

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–148
Figure 1–118. Dynamic Switch Signaling in PCIe ×8 Mode
Stratix IV Device Handbook Volume 2: Transceivers
Fabric
FPGA
Interface
Interface
rateswitch
PIPE
PIPE
collision of the phase compensation FIFO pointers, the PCIe rateswitch controller
automatically disables and resets the phase compensation FIFO pointers of all bonded
channels during clock switch. When the PCIe clock switch circuitry in the local clock
divider indicates successful clock switch completion, the PCIe rateswitch controller
releases the phase compensation FIFO pointer resets.
Figure 1–118
(5 Gbps) data rate.
reset_int
reset_int
reset_int
reset_int
Compensation
Compensation
Compensation
Compensation
Transceiver
Transceiver
Transmitter
Transmitter
Controller
Receiver
Receiver
Express
Phase
Phase
Phase
Phase
Switch
PCS
FIFO
FIFO
PCS
FIFO
FIFO
Rate
PCI
Dynamic Switch Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signaling Rates in PCIe
×8 Mode
CCU
shows the PCIe rateswitch circuitry in PCIe ×8 mode configured at Gen2
rx_locktorefclk
rx_freqlocked
rx_locktodata
signal detect
rx_datain
rx_cruclk
rx_datain
rx_cruclk
CMU0
CMU1
PLL
PLL
rx_locktorefclk
rx_freqlocked
rx_locktodata
signal detect
/1, /2, /4
/1, /2, /4
pcie_gen2switch_done
pcie_gen2switch
/2
/2
Frequency
Frequency
Controller
Controller
LTR/LTD
Detector
Detector
LTR/LTD
Detector
Detector
pcie_gen2switch
Phase
Phase
Phase
Phase
(PD)
(PD)
(PD)
(PD)
Clock and Data Recovery (CDR) Unit
Clock and Data Recovery (CDR) Unit
/1, /2, /4
rateswitch_asn
CMU0 Clock Divider
CMU1 Clock Divider
/1, /2, /4
pcie_gen2switch
Chapter 1: Transceiver Architecture in Stratix IV Devices
Clock Switch
PCI Express
rateswitch_asn
Circuitry
Loop Filter
Loop Filter
Pump +
Pump +
Charge
Charge
/4, /5, /8, /10
1
0
1
0
V
V
/M
/M
CO
CO
CMU0_Channel
CMU1_Channel
/2
/2
/4, /5, /8, /10
February 2011 Altera Corporation
PCI Express Clock Switch Circuitry
/L
/L
Transceiver Block Architecture
Master Transceiver Block
Slave Transceiver Block
in the Master and Slave
the Master and Slave
Bonded Channels in
Low-Speed Parallel
Transceiver Blocks
Transceiver Blocks
Clock to the Eight
High-Speed Serial
Bonded Channels
Clock to the Eight
Recovered
Recovered
Recovered
Recovered
Parallel
Parallel
Serial
Clock
Clock
Serial
Clock
Clock