EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 484

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–40
Stratix IV Device Handbook Volume 2: Transceivers
Receiver Channel Datapath
This section describes the Stratix IV GX and GT receiver channel datapath
architecture. The sub-blocks in the receiver datapath are described in order from the
serial receiver input buffer to the receiver phase compensation FIFO buffer at the
FPGA fabric-transceiver interface.
channel datapath in Stratix IV GX and GT devices.
The receiver channel PMA datapath consists of the following blocks:
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The receiver channel PCS datapath consists of the following blocks:
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■
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■
■
■
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The receiver datapath is very flexible and allows multiple configurations, depending
on the selected functional mode. You can configure the receiver datapath using the
ALTGX MegaWizard Plug-In Manager.
Receiver Input Buffer
The Stratix IV GX and GT receiver input buffers are architecturally similar to each
other. They both support programmable common mode voltage (Rx VCM),
equalization, DC gain, and on-chip termination (OCT) settings.
supported settings of the receiver input buffers in Stratix IV GX and GT devices.
The receiver input buffer receives serial data from the rx_datain port and feeds it to
the CDR unit. In the reverse serial loopback (pre-CDR) configuration, it also feeds the
received serial data to the transmitter output buffer.
input buffer.
Receiver input buffer
Clock and data recovery (CDR) unit
Deserializer
Word aligner
Deskew FIFO
Rate match (clock rate compensation) FIFO
8B/10B decoder
Byte deserializer
Byte ordering
Receiver phase compensation FIFO
PCIe interface
Figure 1–12 on page 1–17
Chapter 1: Transceiver Architecture in Stratix IV Devices
Figure 1–36
shows the receiver
February 2011 Altera Corporation
Table 1–17
Transceiver Block Architecture
shows the receiver
lists the