EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 490

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–46
Table 1–20. Settings for a Stratix II GX to Stratix IV GX DC-Coupled Link
Stratix IV Device Handbook Volume 2: Transceivers
600-6375 Mbps
Note to
(1) V
Data Rate
from 600 Mbps to 6375 Mbps.
CCH
Table
= 1.5 V with TX V
1–20:
Transmitter (Stratix II GX) Settings
(1.5 V PCML)
V
CM
Figure 1–40
(PCML) coupled link.
Figure 1–40. Stratix II GX Transmitter (PCML) to Stratix IV GX Receiver (PCML)
Note to
(1) R
Table 1–20
Stratix IV GX DC-coupled link.
CCH
1.5 V
= 0.7 V can support data rates from 600 Mbps to 3125 Mbps. V
(1)
S
is the parasitic resistance present in the on-chip RX termination and biasing circuitry.
Figure
lists the allowed transmitter and receiver settings in a Stratix II GX to
Stratix II GX
Transmitter
50/60/75-
TX Termination
1–40:
TX V
0.6 V/0.7 V
shows the Stratix II GX transmitter (PCML) to Stratix IV GX receiver
V
CCH
CM
= 1.2 V/1.5 V
Ω
(1)
TX
V
CM
100/120/150 Ω
Termination
Differential
50/60/75-
TX Termination
0.6 V/0.7 V
Physical Medium
Physical Medium
Ω
600-6375 Mbps
42.5/50/60/75-
RX Termination
Chapter 1: Transceiver Architecture in Stratix IV Devices
Data Rate
CCH
= 1.5 V with TX V
Receiver (Stratix IV GX) Settings
Ω
RX
V
CM
R
s
RX V
0.82 V
0.82 V
February 2011 Altera Corporation
42.5/50/60/75-
RX Termination
CM
(1)
= 0.6 V can support data rates
CM
Transceiver Block Architecture
Stratix IV GX
Receiver
Ω
100/120/150 Ω
Termination
Differential