EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 821

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Reset Control and Power Down in Stratix IV Devices
Transceiver Reset Sequences
Table 4–6. Reset and Power-Down Sequences for Bonded Channel Configurations (Part 1 of 2)
February 2011 Altera Corporation
Transmitter Only
Receiver Only
Receiver Only
Channel Set Up
As shown in
steps:
1. After power up, assert pll_powerdown for a minimum period of t
2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and
3. After the transmitter PLL locks, as indicated by the pll_locked signal going high
4. Wait for the rx_pll_locked signal from each channel to go high. The
5. In a bonded channel group, when the rx_pll_locked signal of all the channels has
6. De-assert rx_digitalreset at least t
Non-Bonded Channel Configuration
In non-bonded channels, each channel in the ALTGX MegaWizard Plug-In Manager
instance contains its own tx_digitalreset, rx_analogreset, rx_digitalreset,
rx_pll_locked, and rx_freqlocked signals.
You can reset each channel independently. For example, if there are four non-bonded
channels, the ALTGX MegaWizard Plug-In Manager provides four each of the
following signals: tx_digitalreset, rx_analogreset, rx_digitalreset,
rx_pll_locked, and rx_freqlocked.
Table 4–6
configuration under the stated functional modes.
time between markers 1 and 2).
rx_locktorefclk signals asserted and the rx_locktodata signal de-asserted
during this time period. After you de-assert the pll_powerdown signal, the
transmitter PLL starts locking to the transmitter input reference clock.
(marker 3), de-assert the tx_digitalreset signal (marker 4). For the receiver
operation, after de-assertion of the busy signal, wait for a minimum of two parallel
clock cycles to de-assert the rx_analogreset signal. After the rx_analogreset
signal is de-asserted, the receiver CDR of each channel starts locking to the
receiver input reference clock because rx_locktorefclk is asserted.
rx_pll_locked signal of each channel may go high at different times with respect
to each other (indicated by the slashed pattern at marker 7).
gone high, from that point onwards, wait for at least t
de-assert rx_locktorefclk and assert rx_locktodata (marker 8). At this point, the
receiver CDR of all the channels enters into lock-to-data mode and starts locking to
the received data.
after asserting the rx_locktodata signal.
Basic ×4
Automatic lock mode
Manual lock mode
lists the reset and power-down sequences for one channel in a non-bonded
Receiver CDR Mode
Figure
4–7, for the receiver CDR in manual lock mode, follow these reset
“Transmitter Only Channel” on page 4–16
“Receiver Only Channel—Receiver CDR in Automatic
Lock Mode” on page 4–16
“Receiver Only Channel—Receiver CDR in Manual Lock
Mode” on page 4–17
LTD_M anual
Stratix IV Device Handbook Volume 2: Transceivers
(the time between markers 8 and 9)
LTR_LTD_Manual
Refer to
pll_powerdown
, then
(the
4–15