EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 168

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

5–52
Figure 5–43. Dynamic Phase Shifting Waveform
Stratix IV Device Handbook Volume 1
SCANCLK
PHASESTEP
PHASEUPDOWN
PHASECOUNTERSELECT
PHASEDONE
f
1
You can repeat dynamic phase-shifting indefinitely. For example, in a design where
the VCO frequency is set to 1000 MHz and the output clock frequency is 100 MHz,
performing 40 dynamic phase shifts (each one yields 125 ps phase shift) results in
shifting the output clock by 180°, which is a phase shift of 5 ns.
The PHASESTEP signal is latched on the negative edge of SCANCLK. In
shown by the second SCANCLK falling edge. PHASESTEP must stay high for at least two
SCANCLK cycles. On the second SCANCLK rising edge after PHASESTEP is latched (the
fourth SCANCLK rising edge in
PHASECOUNTERSELECT are latched and the PLL starts dynamic phase-shifting for the
specified counter(s) and in the indicated direction. On the fourth SCANCLK rising edge,
PHASEDONE goes from high to low and remains low until the PLL finishes dynamic
phase-shifting. You can perform another dynamic phase shift after the PHASEDONE
signal goes from low to high.
Depending on the VCO and SCANCLK frequencies, PHASEDONE low time may be greater
than or less than one SCANCLK cycle.
After PHASEDONE goes from low to high, you can perform another dynamic phase shift.
PHASESTEP pulses must be at least one SCANCLK cycle apart.
For information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager, refer
to the
Guide.
Phase-Locked Loops Reconfiguration (ALTPLL_RECONFIG) Megafunction User
a
t
CONFIGPHASE
b
PHASEDONE goes low synchronous with SCANCLK
Figure
5–43), the values of PHASEUPDOWN and
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
c
d
February 2011 Altera Corporation
Figure
PLLs in Stratix IV Devices
5–43, this is