EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 781

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EP4SE530H35C2N

Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H35C2N

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Transceiver Channels in Basic (PMA Direct) Configurations
February 2011 Altera Corporation
Example 5
Consider a design example configuration with a Basic (PMA Direct) ×1 instance with
the number of channels set to 7 in the ALTGX MegaWizard Plug-In Manager. With
this setting, the ALTGX MegaWizard Plug-In Manager provides 7 bits of
gxb_powerdown, rx_analogreset, and pll_powerdown ports.
In this case, the Quartus II software attempts to combine the five channels in the
instance to one transceiver block and the remaining two channels to the second
transceiver block, assuming that the gxb_powerdown and pll_powerdown ports for the
five channels are driven from the same logic.
conditions before and after compilation.
Figure 3–12. Logical View of the Instance with Seven Channels Before Compilation for
Example 5
Receiver and Transmitter configuration:
Basic (PMA Direct) x1 mode
Number of channels = 7
Inst0
Figure 3–12
Stratix IV Device Handbook Volume 2: Transceivers
and
CMU PLL
Figure 3–13
show the
3–27

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