EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 784

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EP4SE530H35C2N

Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H35C2N

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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3–30
Stratix IV Device Handbook Volume 2: Transceivers
Figure 3–14
before compilation.
Figure 3–14. Logical View of the Instances in Basic (PMA Direct) ×1 and Non-Basic (PMA Direct)
Configurations Before Compilation for Example 6
Figure 3–15
after compilation.
Figure 3–15. Combining Basic (PMA-Direct) ×1 and Non-Basic (PMA Direct) Configurations After
Compilation for Example 6
shows Basic (PMA Direct) ×1 and non-Basic (PMA Direct) configurations
shows Basic (PMA Direct) ×1 and non-Basic (PMA Direct) configurations
Inst1: Basic (PMA Direct) x1 mode
Inst0: GIGE functional mode
Number of channels = 4
Number of channels = 1
RX
Inst0: GIGE channel
RX
RX
RX
RX
Inst1: Channel 1
Inst1: Channel 0
Inst1: Channel 3
Inst1: Channel 2
Transceiver Block
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
TX
TX
TX
TX
TX
Combining Transceiver Channels in Basic (PMA Direct) Configurations
CMU PLL
CMU PLL
February 2011 Altera Corporation
(1.25 G)
(1.25 G)
(1.25 Gbps)
CMU PLL

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