EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 381

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Device Configuration Pins
Table 10–12. Dedicated JTAG Pins
April 2011 Altera Corporation
TDI
TDO
TMS
TCK
TRST
Name
Pin
Mode
User
N/A
N/A
N/A
N/A
N/A
f
Test mode
Test clock
Test reset
(optional)
Pin Type
Test data
Test data
Table 10–12
during configuration to prevent accidental loading of JTAG instructions. The TDI,
TMS, and TRST pins have weak internal pull-up resistors, while TCK has a weak
internal pull-down resistor (typically 25 k Ω ). If you plan to use the SignalTap
embedded logic array analyzer, you must connect the JTAG pins of the Stratix IV
device to a JTAG header on your board.
For more information about the pin connection recommendations, refer to the
Stratix IV GX and Stratix IV E Device Family Pin Connection
output
select
input
input
input
Serial input pin for instructions as well as test and programming data. Data is shifted on
the rising edge of TCK. The TDI pin is powered by the 2.5-V/3.0-V V
If the JTAG interface is not required on your board, you can disable the JTAG circuitry by
connecting this pin to logic high using a 1-kΩ resistor.
Serial data output pin for instructions as well as test and programming data. Data is
shifted out on the falling edge of TCK. The pin is tri-stated if data is not being shifted out of
the device. The TDO pin is powered by V
JTAG chain with multiple voltages across the devices in the chain, refer to the
Boundary Scan Testing in Stratix IV Devices
If the JTAG interface is not required on your board, you can disable the JTAG circuitry by
leaving this pin unconnected.
Input pin that provides the control signal to determine the transitions of the TAP controller
state machine. TMS is evaluated on the rising edge of TCK. Therefore, you must set up TMS
before the rising edge of TCK. Transitions within the state machine occur on the falling
edge of TCK after the signal is applied to TMS. The TMS pin is powered by 2.5-V/3.0-V
V
If the JTAG interface is not required on your board, you can disable the JTAG circuitry by
connecting this pin to logic high using a 1-kΩ resistor.
Clock input to the BST circuitry. Some operations occur at the rising edge, while others
occur at the falling edge. The TCK pin is powered by the 2.5-V/3.0-V V
It is expected that the clock input waveform have a nominal 50% duty cycle.
If the JTAG interface is not required on your board, you can disable the JTAG circuitry by
connecting TCK to GND.
Active-low input to asynchronously reset the boundary-scan circuit. The TRST pin is
optional according to IEEE Std. 1149.1. The TRST pin is powered by the 2.5-V/3.0-V V
supply.
Hold TMS at 1 or keep TCK static while TRST is changed from 0 to 1.
If the JTAG interface is not required on your board, you can disable the JTAG circuitry by
connecting the TRST pin to GND.
CCPD
lists the dedicated JTAG pins. JTAG pins must be kept stable before and
.
Description
CCPD
. For recommendations about connecting a
chapter.
Guidelines.
Stratix IV Device Handbook Volume 1
CCPD
CCPD
supply.
supply.
JTAG
®
10–47
CCPD