EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 899

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–25. .mif write transaction in Channel and CMU PLL Reconfiguration Mode
February 2011 Altera Corporation
logical_channel_address[1:0]
reconfig_address_out[5:0]
reconfig_mode_sel[2:0]
channel_reconfig_done
rx_tx_duplex_sel[1:0]
reconfig_address_en
reconfig_data[15:0]
f
1
reconfig_clk
write_all
For guidelines regarding re-using .mifs, specifying input reference clocks, or using
logical_tx_pll_sel ports, refer to
For more information about reset, refer to the “Reset Sequence when Using Dynamic
Reconfiguration with the Channel and TX PLL select/reconfig Option” section in the
Reset Control and Power Down in Stratix IV Devices
CMU PLL Reconfiguration Mode Details
Use this mode to reconfigure only the CMU PLL without affecting the remaining
blocks of the transceiver channel. When you reconfigure the CMU PLL of a
transceiver block to run at a different data rate, all the transceiver channels listening to
this CMU PLL also are reconfigured to the new data rate.
You cannot dynamically reconfigure a CMU PLL into a CMU channel and vice versa.
For more information about the supported configurations in CMU PLL
reconfiguration mode, refer to
Transmitter PLL Powerdown
During CMU PLL reconfiguration mode, the dynamic reconfiguration controller
automatically powers down the selected CMU PLL until it completes reconfiguration.
The ALTGX_RECONFIG instance does not provide external ports to control the
CMU PLL power down. When you reconfigure the CMU PLL, the pll_locked signal
goes low. Therefore, after reconfiguring the transceiver, wait for the pll_locked signal
from the ALTGX instance before continuing normal operation.
busy
1st 16 bits Don’t care
Addr0
Table 5–5 on page
2nd 16 bits
Addr1
3’b101
2’b01
2’b00
“Special Guidelines” on page
Stratix IV Device Handbook Volume 2: Transceivers
5–19.
chapter.
55th 16 bits
Addr54
Don’t care
5–56.
Addr0
5–53