EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 505

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–50. Bit-Slip Mode in 8-Bit PMA-PCS Interface Mode
February 2011 Altera Corporation
rx_enapatternalign
1
rx_patterndetect
rx_dataout[7:0]
rx_syncstatus
depending on whether the input signal rx_a1a2size is driven low or high,
respectively. In Basic single-width mode, the word aligner looks for the 16-bit word
alignment pattern programmed in the ALTGX MegaWizard Plug-In Manager. The
word aligner aligns the 8-bit word boundary to the first word alignment pattern
received after the rising edge on the rx_enapatternalign signal.
Two status signals, rx_syncstatus and rx_patterndetect, with the same latency as
the datapath, are forwarded to the FPGA fabric to indicate word aligner status. On
receiving the first word alignment pattern after the rising edge on the
rx_enapatternalign signal, both the rx_syncstatus and rx_patterndetect signals
are driven high for one parallel clock cycle synchronous to the MSByte of the word
alignment pattern. Any word alignment pattern received thereafter in the same word
boundary causes only the rx_patterndetect signal to go high for one clock cycle.
For the word aligner to re-synchronize to a new word boundary, you must de-assert
rx_enapatternalign and re-assert it again to create a rising edge. After a rising edge
on the rx_enapatternalign signal, if the word alignment pattern is found in a
different word boundary, the word aligner re-synchronizes to the new word boundary
and asserts the rx_syncstatus and rx_patterndetect signals for one parallel clock
cycle.
Figure 1–50
The LSByte (8'hF6) and the MSByte (8'h28) of the 16-bit word alignment pattern are
received in parallel clock cycles n and n + 1, respectively. The rx_syncstatus and
rx_patterndetect signals are both driven high for one parallel clock cycle
synchronous to the MSByte (8'h28) of the word alignment pattern. After initial word
alignment, the 16-bit word alignment pattern is again received across the word
boundary in clock cycles m, m + 1, and m + 2. The word aligner does not re-align to
the new word boundary because of the lack of a preceding rising edge on the
rx_enapatternalign signal. If you create a rising edge on the rx_enapatternalign
signal before the word alignment pattern is received across clock cycles m, m + 1, and
m + 2, the word aligner re-aligns to the new word boundary, causing both the
rx_syncstatus and rx_patterndetect signals to go high for one parallel clock cycle.
shows word aligner behavior in SONET/SDH OC-12 functional mode.
11110110
n
F6
00101000
n + 1
28
0110xxxx
6x
m
Stratix IV Device Handbook Volume 2: Transceivers
10001111
m + 1
8F
xxxx0010
m + 2
x2
1–61