upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 104

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

104
UBEN, LBEN (output)
DSTB, RD,
WRH, WRL (output)
Notes 1. If the HLDRQ signal is inactive (high level) at this sampling timing, the bus hold state is not entered.
Remarks 1.
A16 to A21 (output)
A1 to A15 (output)
CLKOUT (output)
HLDAK (output)
HLDRQ (input)
ASTB (output)
AD0 to AD15
R/W (output)
WAIT (input)
2. If the bus hold status is entered after a write cycle, a high level may be output momentarily from the
R/W pin immediately before the HLDAK signal changes from high level to low level.
2. The broken line indicates the high-impedance state.
(I/O)
indicates the sampling timing when the number of programmable waits is set to 0.
Address
T1
Address
CHAPTER 4 BUS CONTROL FUNCTION
T2
Data
Figure 4-10. Bus Hold Timing
User’s Manual U12768EJ4V1UD
T3
Note 1
TH
Note 2
TH
Address
TH
TH
Undefined Address
TI
Address
Address
T1