upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 52

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

(10) P100 to P107 (Port 10) ··· 3-state I/O
(11) P110 to P114 (Port 11) ··· 3-state I/O
52
P100 to P107 constitute an 8-bit I/O port that can be set to input or output in 1-bit units.
P100 to P107 can also function as a real-time output port and an address bus (A5 to A12) when memory is
expanded externally.
P100 to P107 can be selected as normal output or N-ch open-drain output.
(a) Port function
(b) Alternate functions
(a) Port function
(b) Alternate functions
P110 to P114 constitute a 5-bit I/O port that can be set to input or output in 1-bit units. However, P114 is fixed as
the XT1 input pin.
P110 to P113 can also function as an address bus (A1 to A4) when memory is expanded externally.
(i)
(ii) A5 to A12 (Address 5 to 12) ··· output
(i)
(ii) XT1 (Crystal for subclock) ··· input
P100 to P107 can be set to input or output in 1-bit units using the port 10 mode register (PM10).
P110 to P114 can be set to input or output in 1-bit units using the port 11 mode register (PM11). However,
P114 is fixed as an input pin.
RTP0 to RTP7 (Real-time output port 0 to 7) ··· output
A1 to A4 (Address 1 to 4) ··· output
These pins comprise a real-time output port.
These comprise the address bus that is used for external access. These pins operate as the A5 to A12
bit address output pins within a 22-bit address. The output changes in synchronization with the rising
edge of the clock in the T1 state of the bus cycle. When the timing sets the bus cycle as inactive, the
previous bus cycle’s address is retained.
These comprise the address bus that is used for external access. These pins operate as the lower 4-bit
address output pins within a 22-bit address. The output changes in synchronization with the rising edge
of the clock in the T1 state of the bus cycle. When the timing sets the bus cycle as inactive, the
previous bus cycle’s address is retained.
This is the pin that connects a resonator for subclock generation.
The external clock can also be input to this pin. At this time, input a clock signal to the XT1 pin and its
inverted signal to the XT2 pin.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U12768EJ4V1UD