upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 237

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Note Set SPT only in master mode. However, SPT must be set and a stop condition generated before the
Caution
Remark
Cautions concerning set timing
• For master reception:
• For master transmission:
• Cannot be set at the same time as STT.
• SPT can be set only when in master mode.
• When WTIM has been set to 0, if SPT is set during the wait period that follows output of eight clocks, note
Condition for clearing (SPT = 0)
• Cleared by instruction
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared by LREL = 1
• When IICE = 0
• Cleared when RESET is input
Set a stop condition during the wait period.
that a stop condition will be generated during the high-level period of the ninth clock.
When a ninth clock must be output, WTIM should be changed from 0 to 1 during the wait period following
output of eight clocks, and SPT should be set during the wait period that follows output of the ninth clock.
SPT
0
1
first stop condition is detected following the switch to operation enable status. For details, see
10.3.13 Cautions.
Bit 0 (SPT) is 0 if it is read immediately after data setting.
When bit 3 (TRC) of IIC status register 0 (IICS0) is set to 1, WREL is set during the ninth
clock and wait is canceled, after which TRC is cleared and the SDA line is set to high
impedance.
Stop condition is not generated.
Stop condition is generated (termination of master device’s transfer).
After the SDA line goes to low level, either set the SCL line to high level or wait until it goes to
high level. Next, after the rated amount of time has elapsed, the SDA line is changed from low
level to high level and a stop condition is generated.
CHAPTER 10
Cannot be set during transfer.
Can be set only during the wait period when ACKE has been set to 0 and slave
has been notified of final reception.
Note that a stop condition cannot be generated normally during the ACK period.
User’s Manual U12768EJ4V1UD
Note
SERIAL INTERFACE FUNCTION
Stop Condition Trigger
Condition for setting (SPT = 1)
• Set by instruction
(4/4)
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