upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 122

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

5.3.4 Interrupt control register (xxICn)
maskable interrupt request. The interrupt control register can be read/written in 8-bit or 1-bit units.
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An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each
Cautions 1. If the following three conditions conflict, interrupt servicing will be performed twice. However,
2. Read the xxIFn bit of the xxICn register with interrupts disabled. When the xxIFn bit is read
interrupt servicing is not performed twice if DMA is not being used.
• Execution of bit manipulation instruction for interrupt request flag (xxIFn)
• Interrupt request generated by the same hardware interrupt control register (xxICn) as the
• DMA activated during execution of bit manipulation instruction for interrupt request flag
Two software-based countermeasures are shown below.
with interrupts enabled, a normal value may not be read if the interrupt acknowledgement
timing and the bit reading timing conflict.
interrupt request flag (xxIFn)
(xxIFn)
Insert the DI and EI instructions before and after (respectively) the software bit
manipulation instruction to avoid jumping to an interrupt immediately after execution of
the bit manipulation instruction.
Because interrupts are disabled (DI state) by hardware after an interrupt request has been
acknowledged, clear the interrupt request flag (xxIFn) before executing the EI instruction in
each interrupt servicing routine.
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User’s Manual U12768EJ4V1UD