upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 424

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upd70f3017ay

Manufacturer Part Number
upd70f3017ay
Description
V850/sa1tm 32-/16-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Cautions 1. If an interrupt request or a DMA request is acknowledged between the time PRCMD is
Cautions 2. Always stop the DMA prior to accessing specific registers.
The following sequence shows the data setting of the FLPMC register.
No special sequence is required when reading the FLPMC register.
<1> Disable DMA operation.
<2> Set the PSW NP bit to 1 (interrupts disabled).
<3> Write any 8-bit data in the command register (PRCMD).
<4> Write the set data in the FLPMC register (using the following instructions).
<5> Return the PSW NP bit to 0 (interrupt disable canceled).
<6> Insert five NOP instructions (when manipulating the FLSPM bit).
<7> If necessary, enable DMA operation.
• Store instruction (ST/SST instruction)
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
generated (<3>) and the FLPMC register write operation (<4>) that follows immediately after,
the write operation to the FLPMC register is not performed and a protection error (PRERR bit
of SYS register is 1) may occur. Therefore, set the NP bit of the PSW to 1 (<2>) to disable the
acknowledgement of INT/NMI or to disable DMA transfer.
The above also applies when a bit manipulation instruction is used to set the FLPMC
register.
A description example is given below.
[Description example]
LDSR rX.5
ST.B
ST.B
LDSR rY, 5
NOP
NOP
NOP
NOP
NOP
(next instruction)
When saving the value of the PSW, the value of the PSW prior to setting the NP bit must be
transferred to the rY register.
rX: Value to be written to PSW
rY: Value to be written back to PSW
rD: Value to be set to FLPMC
r0, PRCMD [r0] ; Write to PRCMD
rD, FLPMC [r0] ; FLPMC register setting
.
.
.
CHAPTER 16 FLASH MEMORY
User’s Manual U12768EJ4V1UD
; NP bit = 1
; NP bit = 0
; Dummy instruction (5 instructions, when
; Execution routine following cancellation of
manipulating FLSPM bit)
IDLE/software STOP mode

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