upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 74

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

(3) On-chip peripheral I/O area
74
Cautions 1. The least significant bit of an address is not decoded since all registers reside at an even
A 4 KB area of addresses FFF000H to FFFFFFH is reserved as an on-chip peripheral I/O area.
The V850/SA1 is provided with a 1 KB area of addresses FFF000H to FFF3FFH as a physical on-chip peripheral
I/O area, and its image can be seen on the rest of the area (FFF400H to FFFFFFH).
Peripheral I/O registers associated with operation mode specification and state monitoring for the on-chip
peripherals are all memory-mapped to the on-chip peripheral I/O area. Program fetches are not allowed in this
area.
2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8
3. If a register at address n that can be accessed only in halfword units is accessed in word
4. If a register at address n that can be accessed in word units is accessed with a word
5. Addresses that are not defined as registers are reserved for future expansion. If these
address. If an odd address (2n + 1) in the peripheral I/O area is referenced (accessed in
byte units), the register at the next lowest even address (2n) will be accessed.
bits become undefined, if the access is a read operation. If a write access is made, only
the data in the lower 8 bits is written to the register.
units, the operation is replaced with two halfword operations. The first operation (lower 16
bits) accesses the register at address n and the second operation (higher 16 bits)
accesses the register at address n + 2.
operation, the operation is replaced with two halfword operations. The first operation
(lower 16 bits) accesses the register at address n and the second operation (higher 16 bits)
accesses the register at address n + 2.
addresses are accessed, the operation is undefined and not guaranteed.
xxFFFFFFH
xxFFFC00H
xxFFFBFFH
xxFFF7FFH
xxFFF3FFH
xxFFF800H
xxFFF400H
xxFFF000H
Figure 3-12. On-Chip Peripheral I/O Area
Image
Image
Image
Image
CHAPTER 3 CPU FUNCTIONS
User’s Manual U12768EJ4V1UD
Physical on-chip
Peripheral I/O
peripheral I/O
3FFH
000H