upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 21

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

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Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master
and Slave) ..................................................................................................................................................... 283
Block Diagram of UARTn .............................................................................................................................. 287
Settings of ASIMn (Operation Stop Mode) .................................................................................................... 294
ASIMn Setting (UART Mode) ........................................................................................................................ 295
ASISn Setting (UART Mode) ......................................................................................................................... 296
BRGCn Setting (UART Mode)....................................................................................................................... 297
BRGMC0 and BRGMC01 Settings (UART Mode) ......................................................................................... 298
BRGMC1 Settings (UART Mode) .................................................................................................................. 299
Error Tolerance (When k = 16), Including Sampling Errors ........................................................................... 301
Format of Transmit/Receive Data in Asynchronous Serial Interface ............................................................. 302
Timing of Asynchronous Serial Interface Transmit Completion Interrupt ....................................................... 304
Timing of Asynchronous Serial Interface Receive Completion Interrupt ........................................................ 305
Receive Error Timing..................................................................................................................................... 306
Block Diagram of A/D Converter.................................................................................................................... 309
Basic Operation of A/D Converter ................................................................................................................. 317
Relationship Between Analog Input Voltage and A/D Conversion Result...................................................... 318
A/D Conversion by Hardware Start (with Falling Edge Specified) ................................................................. 320
A/D Conversion by Software Start ................................................................................................................. 321
Handling of Analog Input Pin ......................................................................................................................... 323
A/D Conversion End Interrupt Request Generation Timing ........................................................................... 324
Handling of AV
Overall Error .................................................................................................................................................. 326
Quantization Error ......................................................................................................................................... 327
Zero-Scale Error ............................................................................................................................................ 327
Full-Scale Error ............................................................................................................................................. 328
Differential Linearity Error.............................................................................................................................. 328
Integral Linearity Error ................................................................................................................................... 329
Sampling Time .............................................................................................................................................. 329
Block Diagram of DMAC................................................................................................................................ 331
Correspondence Between DRAn Setting Value and Internal RAM (4 KB)..................................................... 333
Correspondence Between DRAn Setting Value and Internal RAM (8 KB)..................................................... 334
DMA Transfer Operation Timing.................................................................................................................... 338
Processing When Transfer Requests DMA0 to DMA2 Are Generated Simultaneously................................. 339
Block Diagram of RTO................................................................................................................................... 341
Configuration of Real-Time Output Buffer Registers ..................................................................................... 342
Example of Operation Timing of RTO (When EXTR = 0, BYTE = 0) ............................................................. 346
DD
Pin ..................................................................................................................................... 325
LIST OF FIGURES (4/6)
User’s Manual U12768EJ4V1UD
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