upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 35

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

1.6.2 Internal units
(1) CPU
(2) Bus control unit (BCU)
(3) ROM
(4) RAM
(5) Interrupt controller (INTC)
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
PD703014A, 703014AY, 703014B, 703014BY
PD703015A, 703015AY, 703015B, 703015BY
PD70F3015B, 70F3015BY
PD703017A, 703017AY
PD70F3017A, 70F3017AY
PD703014A, 703014AY, 703015B, 703015BY
PD703015A, 703015AY, 703015B, 703015BY
PD70F3015B, 703015BY
PD703017A, 703017AY
PD70F3017A, 70F3017AY
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic
operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits) and the 32-bit barrel shifter
help accelerate processing of complex instructions.
The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an
instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU
generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an
instruction queue.
This consists of a mask ROM or flash memory mapped to the address space starting at 00000000H.
ROM can be accessed by the CPU in one clock cycle during instruction fetch. The internal ROM capacity and
internal ROM area vary as follows according to the product.
The internal RAM capacity and internal RAM area vary as follows according to the product. RAM can be
accessed by the CPU in one clock cycle during data access.
This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral hardware and
external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiple
servicing control can be performed for interrupt sources.
Product Name
Product Name
CHAPTER 1 INTRODUCTION
User’s Manual U12768EJ4V1UD
64 KB (mask ROM)
128 KB (mask ROM)
128 KB (flash memory)
256 KB (mask ROM)
256 KB (flash memory)
4 KB
8 KB
Internal ROM Capacity
Internal RAM Capacity
xx000000H to xx00FFFFH
xx000000H to xx01FFFFH
xx000000H to xx03FFFFH
xxFFE000H to xxFFEFFFH
xxFFD000H to xxFFEFFFH
Internal ROM Area
Internal RAM Area
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