upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 115

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

5.3 Maskable Interrupts
interrupt sources (refer to 5.1.1 Features).
the default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt
control registers, allowing programmable priority control.
and the interrupt disabled (DI) status is set.
enables interrupts having a higher priority to immediately interrupt the current service routine in progress. Note that
only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested.
instruction, and restore EIPC and EIPSW to the original values by executing the DI instruction before the RETI
instruction.
interrupt functions as a maskable interrupt (INTWDTM).
5.3.1 Operation
handler routine.
1 or PSW.ID = 1) are internally held pending. When the interrupts are unmasked, or when PSW.NP = 0 and PSW.ID
= 0 by using the RETI and LDSR instructions, the pending INT is input to start the new maskable interrupt servicing.
Maskable interrupt requests can be masked by interrupt control registers.
If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to
When an interrupt request has been acknowledged, the acknowledgement of other maskable interrupts is disabled
When the EI instruction is executed in an interrupt servicing routine, the interrupt enabled (EI) status is set which
To use multiple interrupts, it is necessary to save EIPC and EIPSW to memory or a register before executing the EI
When the WDTM4 bit of the watchdog timer mode register (WDTM) is set to 0, the watchdog timer overflow
If a maskable interrupt occurs by INT input, the CPU performs the following processing, and transfers control to a
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower halfword of ECR (EICC).
<4> Sets the ID bit of the PSW and clears the EP bit.
<5> Loads the corresponding handler address to the PC, and transfers control.
The INT input masked by INTC and the INT input that occurs during the other interrupt servicing (when PSW.NP =
How the maskable interrupts are serviced is shown below.
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User’s Manual U12768EJ4V1UD
The V850/SA1 has 30 maskable
115