upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 105

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

4.9 Bus Priority
(continuous). The bus hold cycle is given the highest priority, followed by memory access, instruction fetch (branch),
and instruction fetch (continuous) in that order.
access.
access operations.
4.10 Memory Boundary Operation Conditions
4.10.1 Program space
(1) Do not execute a branch to the on-chip peripheral I/O area or continuous fetch from the internal RAM area to
(2) A prefetch operation straddling over the on-chip peripheral I/O area (invalid fetch) does not take place if a branch
4.10.2 Data space
boundary (when the lowest 2 bits of the address are “0”) is accessed by halfword (16 bits)/word (32 bits) data.
Therefore, access that straddles over the memory or memory block boundary does not take place.
For details, refer to V850 Series Architecture User’s Manual.
There are four external bus cycles: bus hold, memory access, instruction fetch (branch), and instruction fetch
The instruction fetch cycle may be inserted between the read access and write access in a read-modify-write
No instruction fetch cycle is inserted between the lower halfword access and higher halfword access of word
Only the address aligned at the halfword boundary (when the least significant bit of the address is “0”)/word
peripheral I/O area. If a branch or instruction fetch is executed, the NOP instruction code is continuously fetched
and no data is fetched from external memory.
instruction exists at the upper-limit address of the internal RAM area.
CHAPTER 4 BUS CONTROL FUNCTION
Bus hold
Memory access
Instruction fetch (branch)
Instruction fetch (continuous)
External Bus Cycle
User’s Manual U12768EJ4V1UD
Table 4-3. Bus Priority
Priority
1
2
3
4
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