upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 269

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

10.3.6 Interrupt request (INTIIC0) generation timing and wait control
and the corresponding wait control, as shown below.
(1) During address transmission/reception
(2) During data reception
(3) During data transmission
(4) Wait cancellation method
(5) Stop condition detection
The setting of bit 3 (WTIM) of IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated
Notes 1.
Remark
WTIM
• Slave device operation:
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM bit.
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM bit.
The four wait cancellation methods are as follows.
• By setting bit 5 (WREL) of IIC control register 0 (IICC0) to 1
• By writing to IIC shift register 0 (IIC0)
• By setting start condition (bit 1 (STT) of IIC control register 0 (IICC0) = 1)
• By setting stop condition (bit 0 (SPT) of IIC control register 0 (IICC0) = 1)
When an 8-clock wait has been selected (WTIM = 0), the output level of ACK must be determined prior to wait
cancellation.
INTIIC0 is generated when a stop condition is detected.
0
1
2.
The numbers in the table indicate the number of the serial clock signals. Interrupt requests and wait
control are both synchronized with the falling edge of these clock signals.
The slave device’s INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when
there is a match with the address set to the slave address register (SVA0).
At this point, ACK is output regardless of the value set to bit 2 (ACKE) of IICC0. For a slave device that
has received an extension code, INTIIC0 occurs at the falling edge of the eighth clock.
If the received address does not match the contents of the slave address register (SVA0), neither
INTIIC0 nor a wait occurs.
Address
9
9
Notes 1, 2
Notes 1, 2
During Slave Device Operation
Table 10-3. INTIICn Generation Timing and Wait Control
WTIM bit.
Interrupt and wait timing are determined regardless of the WTIM bit.
Data Reception
CHAPTER 10
8
9
Note 2
Note 2
User’s Manual U12768EJ4V1UD
SERIAL INTERFACE FUNCTION
Data Transmission
8
9
Note 2
Note 2
Address
9
9
During Master Device Operation
Data Reception
8
9
Data Transmission
8
9
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