upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 148

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

6.4.4 Software STOP mode
(1) Settings and operating states
(2) Release of software STOP mode
148
Port function
External bus interface
External
interrupt
request
In
external
expansion
mode
Item
This mode stops the entire system by stopping the main clock oscillator to stop supplying the internal main clock.
The subclock oscillator continues operating and the on-chip subclock supply is continued.
When the subclock is not used, low power consumption of only the current flowing through the on-chip feed-back
resistor and leakage current is realized.
In this mode, program execution is stopped and the contents of all registers and internal RAM are retained as
they were just before software STOP mode was set. On-chip peripheral functions also stop operation (peripheral
functions operating on the subclock are not stopped).
acknowledged.
This mode can be set only when the main clock is being used as the CPU clock. This mode is set when the STP
bit in the power save control register (PSC) has been set to 1.
Do not set this mode when the subclock has been selected as the CPU clock.
The operating statuses in software STOP mode are listed in Table 6-3.
Software STOP mode can be released by a non-maskable interrupt, an unmasked interrupt request output from
an on-chip peripheral I/O that can be operated, or RESET input.
When the software STOP mode is released, the oscillation stabilization time is secured.
IDLE Mode Settings
NMI
INTP0 to INTP3
INTP4 to INTP6
AD0 to AD15
A16 to A21
LBEN, UBEN
R/W
DSTB, WRL,
WRH, RD
ASTB
HLDAK
Held
Stopped
Operating
Operating
Stopped
High impedance
Table 6-2. Operating Statuses in IDLE Mode (2/2)
CHAPTER 6 CLOCK GENERATION FUNCTION
When Subclock Exists
User’s Manual U12768EJ4V1UD
External bus hold requests (HLDRQ) are not
When Subclock Does Not Exist