upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 174
upd70f3017ay
Manufacturer Part Number
upd70f3017ay
Description
V850/sa1tm 32-/16-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3017AY.pdf
(492 pages)
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(4) Pulse width measurement by restarting
174
When the valid edge of the TIn0 pin is detected, the pulse width of the signal input to the TIn0 pin can be
measured by clearing 16-bit timer register n (TMn) once and then resuming counting after loading the count value
of TMn to 16-bit capture/compare register n1 (CRn1) (See Figure 7-13).
The edge is specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register n (PRMn). The rising or
falling edge can be specified.
The valid edge is detected by sampling at the count clock cycle selected by prescaler mode register n, n1 (PRMn,
PRMn1) and the capture operation is not performed until the valid level is detected two times. Therefore, noise
with a short pulse width can be eliminated.
Remark
Caution If the valid edge of the TIn0 pin is specified to be both the rising and falling edges,
Remark
TIn0 pin input
Value loaded
Value loaded
Count clock
TMn count
INTTMn1
Figure 7-13. Timing of Pulse Width Measurement with Free-Running Counter and
to CRn1
to CRn0
OVFn
capture/compare register n0 (CRn0) cannot perform its capture operation.
n = 0, 1
value
n = 0, 1
0000H 0001H
t
Two Capture Registers (with Rising Edge Specified)
CHAPTER 7 TIMER/COUNTER FUNCTION
D0
(D1
D0
D0 + 1
User’s Manual U12768EJ4V1UD
–
D0) × t
D1 D1 + 1
D1
(10000H
–
FFFFH 0000H
D1 + D2) × t
D2
(D3
D2
D2 + 1
–
D2) × t
D3
D3
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