upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 96

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

4.7 Bus Hold Function
4.7.1 Outline of function
P95 and P96 become valid.
the external address/data bus and strobe pins go into a high-impedance state
status). When the HLDRQ pin becomes inactive (high) indicating that the request for the bus is cleared, these pins
are driven again. During the bus hold period, the internal operation continues until the next external memory access.
configuration is used and when a DMA controller is connected.
access and write access in a read-modify-write access executed using a bit manipulation instruction.
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When the MM3 bit of the memory expansion mode register (MM) is set (1), the HLDRQ and HLDAK pin functions of
When the HLDRQ pin becomes active (low) indicating that another bus master is requesting acquisition of the bus,
The bus hold status can be recognized by the HLDAK pin becoming active (low).
This feature can be used to design a system where two or more bus masters exist, such as when a multi-processor
A bus hold request is not acknowledged between the first and the second word access, and between the read
Note The A1 to A15 pins are set to the hold state when a separate bus is used.
CHAPTER 4 BUS CONTROL FUNCTION
User’s Manual U12768EJ4V1UD
Note
, and the bus is released (bus hold