upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 241

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

(3) IIC clock select register 0 (IICCL0), IIC function expansion register 0 (IICX0)
After reset: 00H
After reset: 00H
The IICCL0 and IICX0 registers are used to set the transfer clock for the I
The IICCL0 and IICX0 registers can be set by an 8-bit or 1-bit memory manipulation instruction.
RESET input sets these registers to 00H.
Note Bits 4 and 5 of the IICCL0 register are read-only bits.
Caution Be sure to set bits 6 and 7 of the IICCL0 register to 0.
Remark
IICCL0
IICX0
Condition for clearing (CLD = 0)
• When the SCL line is at low level
• When IICE = 0
• When RESET is input
Condition for clearing (DAD = 0)
• When the SDA line is at low level
• When IICE = 0
• When RESET is input
A digital filter can be used only in high-speed mode.
The transfer clock does not change by setting DFC on/off in the high-speed mode.
SMC
DAD
DFC
CLD
0
1
0
1
0
1
0
1
IICE: Bit 7 of IIC control register 0 (IICC0)
7
7
0
0
SCL line was detected at low level.
SCL line was detected at high level.
SDA line was detected at low level.
SDA line was detected at high level.
Operated in standard mode
Operated in high-speed mode
Digital filter off
Digital filter on
R/W
R/W
Note
6
0
6
0
CHAPTER 10
Address: FFFFF34AH
Address: FFFFF344H
CLD
Detection of SCL Line Level (Valid Only When IICE = 1)
Detection of SDA Line Level (Valid Only When IICE = 1)
0
5
5
User’s Manual U12768EJ4V1UD
SERIAL INTERFACE FUNCTION
DAD
Operation Control of Digital Filter
0
4
4
Operation Mode Switching
SMC
0
3
3
Condition for setting (CLD = 1)
• When the SCL line is at high level
Condition for setting (DAD = 1)
• When the SDA line is at high level
DFC
2
2
0
2
C bus.
CL1
1
1
0
CLX
CL0
0
0
(1/2)
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