upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 169

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

7.2.3 Pulse width measurement
pins.
synchronization with the edge of the signal input to the TIn0 pin.
(1) Pulse width measurement with free running counter and one capture register
TMCn
CRCn
16-bit timer register n (TMn) can be used to measure the pulse widths of the signals input to the TIn0 and TIn1
Measurement can be carried out with TMn used as a free-running counter or by restarting the timer in
If the edge specified by prescaler mode register n (PRMn) is input to the TIn0 pin when 16-bit timer register n
(TMn) is used as a free-running counter (refer to Figure 7-6), the value of TMn is loaded to 16-bit
capture/compare register n1 (CRn1), and an external interrupt request signal (INTTMn1) is set.
The edge is specified by using bits 6 and 7 (ESn10 and ESn11) of prescaler mode register n (PRMn). The rising
edge, falling edge, or both the rising and falling edges can be selected.
The valid edge is detected by sampling at the count clock cycle selected by prescaler mode register n, n1 (PRMn,
PRMn1), and a capture operation is not performed until the valid level is detected two times. Therefore, noise
with a short pulse width can be eliminated.
Remark
Remark
0
0
n = 0, 1
0/1: When these bits are reset to 0 or set to 1, other functions can be used along with the pulse
Figure 7-6. Control Register Settings for Pulse Width Measurement with
width measurement function.
registers 0, 1 (TMC0, TMC1) and 7.1.4 (2) Capture/compare control registers 0, 1 (CRC0,
CRC1).
0
0
(a) 16-bit timer mode control registers 0, 1 (TMC0, TMC1)
(b) Capture/compare control registers 0, 1 (CRC0, CRC1)
Free-Running Counter and One Capture Register
0
0
CHAPTER 7 TIMER/COUNTER FUNCTION
User’s Manual U12768EJ4V1UD
0
0
TMCn3
For details, refer to 7.1.4 (1) 16-bit timer mode control
0
0
TMCn2
CRCn2
1
1
TMCn1
CRCn1
0/1
0/1
CRCn0
OVFn
0
0
Free-running mode
CRn0 used as compare
register
CRn1 used as capture
register
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