upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 478

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Instruction Set List (3/4)
478
Logic
operation
Jump
Bit
manipulate
Instruction
Notes 1.
Group
2.
XOR
XORI
NOT
SHL
SHL
SHR
SHR
SAR
SAR
JMP
JR
JARL
Bcond
SET1
CLR1
NOT1
TST1
ddddddddddddddddddddd is the higher 21 bits of dip22.
dddddddd is the higher 8 bits of disp9.
Mnemonic
reg1, reg2
imm16,
reg1, reg2
reg1, reg2
reg1, reg2
imm5, reg2 rrrrr010110iiiii
reg1, reg2
imm5, reg2 rrrrr010100iiiii
reg1, reg2
imm5, reg2 rrrrr010101iiiii
[reg1]
disp22
disp22,
reg2
disp9
bit#3,
disp16
[reg1]
bit#3,
disp16
[reg1]
bit#3,
disp16
[reg1]
bit#3,
disp16
[reg1]
Operand
APPENDIX C LIST OF INSTRUCTION SETS
rrrrr001001RRRRR
rrrrr110101RRRRR
iiiiiiiiiiiiiiii
rrrrr000001RRRRR
rrrrr111111RRRRR
0000000011000000
rrrrr111111RRRRR
0000000010000000
rrrrr111111RRRRR
0000000010100000
00000000011RRRR
R
ddddddddddddddd0
rrrrr11110dddddd
ddddddddddddddd0
ddddd1011dddcccc
00bbb111110RRRRR
dddddddddddddddd
10bbb111110RRRR
R
dddddddddddddddd
01bbb111110RRRRR
dddddddddddddddd
11bbb111110RRRRR
dddddddddddddddd
0000011110dddddd
Opcode
User’s Manual U12768EJ4V1UD
Note 1
Note 1
Note 2
GR [reg2] ← GR [reg2] XOR GR [reg1]
GR [reg2] ← GR [reg1] XOR zero-extend
(imm16)
GR [reg2] ← NOT (GR [reg1])
GR [reg2] ← GR [reg2] logically shift left by
GR [reg1]
GR [reg2] ← GR [reg2] logically shift left
by zero-extend (imm5)
GR [reg2] ← GR [reg2] logically shift right
by GR [reg1]
GR [reg2] ← GR [reg2] logically shift right
by zero-extend (imm5)
GR [reg2] ← GR [reg2] arithmetically shift
right by GR [reg1]
GR [reg2] ← GR [reg2] arithmetically shift
right by zero-extend (imm5)
PC ← GR [reg1]
PC ← PC + sign-extend (disp22)
GR [reg2] ← PC + 4
PC ← PC + sign-extend (disp22)
if conditions are satisfied
then PC ← PC + sign-extend (disp9)
adr ← GR [reg1] + sign-extend (disp16)
Z flag ← Not (Load-memory-bit
(adr, bit#3))
Store-memory-bit (adr, bit#3, 1)
adr ← GR [reg1] + sign-extend (disp16)
Z flag ← Not (Load-memory-bit
(adr, bit#3))
Store-memory-bit (adr, bit#3, 0)
adr ← GR [reg1] + sign-extend (disp16)
Z flag ← Not (Load-memory-bit
(adr, bit#3))
Store-memory-bit (adr, bit#3, Z flag)
adr ← GR [reg1] + sign-extend (disp16)
Z flag ← Not (Load-memory-bit (adr, bit#3))
Operation
CY OV S
×
×
×
×
×
×
0
0
0
0
0
0
0
0
0
Flag
×
×
×
×
×
×
×
×
×
Z SAT
×
×
×
×
×
×
×
×
×
×
×
×
×