upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 244

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

10.3.4 I
Figure 10-8 shows the transfer timing for the “start condition”, “data”, and “stop condition” output via the I
serial data bus.
device that receives 8-bit data).
level period can be extended and a wait can be inserted.
(1) Start condition
244
The following section describes the I
The master device outputs the start condition, slave address, and stop condition.
The acknowledge signal (ACK) can be output by either the master or slave device (normally, it is output by the
The serial clock (SCL) is continuously output by the master device. However, in the slave device, the SCL’s low-
The start condition is met when the SCL pin is at high level and the SDA pin changes from high level to low level.
The start conditions for the SCL pin and SDA pin are signals that the master device outputs to the slave device
when starting a serial transfer. The slave device includes hardware for detecting start conditions.
A start condition is output when bit 1 (STT) of IIC control register 0 (IICC0) is set to 1 after a stop condition has
been detected (SPD: Bit 0 = 1 in IIC status register 0 (IICS0)). When a start condition is detected, bit 1 (STD) of
IICS0 is set to 1.
2
C bus definitions and control methods
SDA
SCL
Start
condition
Address
1 to 7
Figure 10-8. I
R/W
CHAPTER 10
8
SDA
SCL
2
C bus’s serial data communication format and the signals used by the I
ACK
9
Figure 10-9 Start Condition
H
User’s Manual U12768EJ4V1UD
2
C Bus’s Serial Data Transfer Timing
SERIAL INTERFACE FUNCTION
1 to 7
Data
8
ACK
9
1 to 7
Data
8
ACK
9
Stop
condition
2
C bus’s
2
C bus.