upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 239

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Condition for clearing (TRC = 0)
• When a stop condition is detected
• Cleared by LREL = 1
• When IICE changes from 1 to 0
• Cleared by WREL = 1
• When ALD changes from 0 to 1
• When RESET is input
Master
• When “1” is output to the first byte’s LSB (transfer
Slave
• When a start condition is detected
When not used for communication
Condition for clearing (EXC = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL = 1
• When IICE changes from 1 to 0
• When RESET is input
Condition for clearing (COI = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL = 1
• When IICE changes from 1 to 0
• When RESET is input
Note
Remark
direction specification bit)
TRC
EXC
COI
0
1
0
1
0
1
When bit 3 (TRC) of IIC status register 0 (IICS0) is 1, if a wait is released by setting bit 5 (WREL) of IIC
control register 0 (IICC0) at the 9th clock, the SDA line becomes high impedance after TRC is cleared.
Extension code was not received.
Extension code was received.
Addresses do not match.
Addresses match.
Receive status (other than transmit status). The SDA line is set to high impedance.
Transmit status. The value in the SO latch is enabled for output to the SDA line (valid starting at the
rising edge of the first byte’s ninth clock).
LREL:
IICE:
Note
Bit 6 of IIC control register 0 (IICC0)
Bit 7 of IIC control register 0 (IICC0)
CHAPTER 10
User’s Manual U12768EJ4V1UD
Detection of Extension Code Reception
Detection of Transmit/Receive Status
Detection of Matching Addresses
SERIAL INTERFACE FUNCTION
Condition for setting (EXC = 1)
• When the higher four bits of the received address
Condition for setting (COI = 1)
• When the received address matches the local
Condition for setting (TRC = 1)
Master
• When a start condition is generated
Slave
• When “1” is input by the first byte’s LSB (transfer
data are either “0000” or “1111” (set at the rising
edge of the eighth clock).
address (SVA0) (set at the rising edge of the eighth
clock).
direction specification bit)
(2/3)
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