upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 248

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

of the SCL’s eighth clock regardless of the ACKE value. No ACK signal is output if the received address is not a local
address.
(5) Stop condition
248
When 8-clock wait is selected:
When 9-clock wait is selected:
When the local address is received, an ACK signal is automatically output in synchronization with the falling edge
The ACK signal output method during data reception is based on the wait timing setting, as described below.
When the SCL pin is at high level, changing the SDA pin from low level to high level generates a stop condition.
A stop condition is a signal that the master device outputs to the slave device when serial transfer has been
completed. The slave device includes hardware that detects stop conditions.
A stop condition is generated when bit 0 (SPT) of IIC control register 0 (IICC0) is set to 1. When the stop
condition is detected, bit 0 (SPD0) of IIC status register 0 (IICS0) is set to 1 and INTIIC0 is generated when bit 4
(SPIE0) of IICC0 is set to 1.
ACK signal is output at the falling edge of the SCL’s eighth clock when ACKE is
set to 1 before wait cancellation.
ACK signal is automatically output at the falling edge of the SCL’s eighth clock if
ACKE has already been set to 1.
CHAPTER 10
SDA
SCL
Figure 10-13. Stop Condition
H
User’s Manual U12768EJ4V1UD
SERIAL INTERFACE FUNCTION