upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 279
upd70f3017ay
Manufacturer Part Number
upd70f3017ay
Description
V850/sa1tm 32-/16-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD70F3017AY.pdf
(492 pages)
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10.3.15 Timing of data communication
devices as its communication partner.
that specifies the data transfer direction and then starts serial communication with the slave device.
The transmit data is transferred to the SO latch and is output (MSB first) via the SDA pin.
When using I
After outputting the slave address, the master device transmits the TRC bit (bit 3 of IIC status register 0 (IICS0))
The shift operation of IIC bus shift register 0 (IIC0) is synchronized with the falling edge of the serial clock (SCL).
Data input via the SDA pin is captured by IIC0 at the rising edge of SCL.
The following shows the timing charts of data communication.
2
C bus mode, the master device outputs an address via the serial bus to select one of several slave
CHAPTER 10
User’s Manual U12768EJ4V1UD
SERIAL INTERFACE FUNCTION
279
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