upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 186

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

(7) Operation of OVFn flag
(8) Conflict operation
(9) Timer operation
186
(a) OVFn flag set
(b) Clear OVFn flag
(a) If the read period and capture trigger input conflict
(b) If the match timing of the write period and TMn conflict
(a) CRn1 capture
Remark
Remark
The OVFn flag is set to 1 in the following case in addition to when the TMn register overflows:
Select the mode in which the timer is cleared and started on a match between TMn and CRn0.
Set the CRn0 register to FFFFH.
When TMn is cleared from FFFFH to 0000H on a match with the CRn0 register.
Even if the OVFn flag is cleared before the next count clock is counted (before TMn becomes 0001H) after
TMn has overflowed, the OVFn flag is set again and the clear becomes invalid.
When 16-bit capture/compare registers n0 and n1 (CRn0, CRn1) are used as capture registers, if the read
period and capture trigger input conflict, the capture trigger has priority. The read data of the CRn0 and
CRn1 registers is undefined.
When 16-bit capture/compare registers n0 and n1 (CRn0, CRn1) are used as capture registers, because
match detection cannot be performed correctly if the match timing of the write period and 16-bit timer register
n (TMn) conflict, do not write to the CRn0 and CRn1 registers close to the match timing.
Even if 16-bit timer register n (TMn) is read, a capture to 16-bit capture/compare register n1 (CRn1) is not
performed.
n = 0, 1
n = 0, 1
↓
↓
Count pulse
INTTMn0
Remark n = 0, 1
OVFn
CRn0
Figure 7-28. Operation Timing of OVFn Flag
TMn
CHAPTER 7 TIMER/COUNTER FUNCTION
FFFEH
User’s Manual U12768EJ4V1UD
FFFFH
FFFFH
0000H
0001H