upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 109

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

5.2 Non-Maskable Interrupts
requests are not subject to priority control and take precedence over all the other interrupts.
0 (EGN0) is detected at the NMI pin, an interrupt occurs.
watchdog timer mode register (WDTM) is set to 1.
another non-maskable interrupt request is held pending. The pending NMI is acknowledged when PSW.NP is cleared
to 0 after the original service routine of the non-maskable interrupt under execution has been terminated (by the RETI
instruction). Note that if two or more NMI requests are input during the execution of the service routine for an NMI, the
number of NMIs that will be acknowledged after PSW.NP goes to ‘‘0’’, is only one.
Non-maskable interrupt requests are acknowledged unconditionally, even in the interrupt disabled (DI) status. NMI
The V850/SA1 includes the following two non-maskable interrupt requests.
• NMI pin input (NMI)
• Non-maskable watchdog timer interrupt request (INTWDT)
When the valid edge specified by rising edge specification register 0 (EGP0) and falling edge specification register
INTWDT functions as the non-maskable interrupt (INTWDT) only in the state in which the WDTM4 bit of the
While the service routine of a non-maskable interrupt is being executed (PSW.NP = 1), the acknowledgement of
Caution Do not clear PSW.NP to 0 by the LDSR instruction during non-maskable interrupt servicing. If
PSW.NP is cleared to 0, the interrupts afterwards cannot be acknowledged correctly.
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User’s Manual U12768EJ4V1UD
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