upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 306

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

306
(v) Receive error
Parity error
Framing error
Overrun error
Receive error
Three types of errors can occur during a receive operation: a parity error, framing error, and overrun error.
When, as the result of data reception, an error flag is set in asynchronous serial interface status register n
(ASISn), the receive error interrupt request (INTSERn) is generated. The receive error interrupt request is
generated prior to the receive completion interrupt request (INTSRn). Table 10-9 shows receive error causes.
By reading the contents of ASISn during receive error interrupt servicing (INTSERn), it is possible to ascertain
which error has occurred during reception (see Table 10-9 and 10.4.2 (2) Asynchronous serial interface
status registers 0 and 1 (ASIS0, ASIS1)
The contents of ASISn are reset (0) by reading the receive buffer register (RXBn) or receiving subsequent
data (if there is an error in the subsequent data, the error flag is set).
Note Even if a receive error occurs when the ISRMn bit of ASIMn is set (1), INTSRn is not generated.
Cautions 1. The contents of asynchronous serial interface status register n (ASISn) are reset (0)
Remark
(When parity error occurs)
2. Be sure to read receive buffer register n (RXBn) even when a receive error occurs.
n = 0, 1
receive buffer register.
Parity specification at transmission and receive data parity do not match.
Stop bit is not detected.
Reception of subsequent data was completed before data was read from the
by reading receive buffer register N (RXBn) or receiving subsequent data. To check
the contents of an error, always read ASISn before reading RXBn.
If RXBn is not read out, an overrun error will occur during subsequent data
reception and as a result receive errors will continue to occur.
RxDn (Input)
INTSRn
INTSERn
INTSERn
CHAPTER 10
Figure 10-34. Receive Error Timing
Table 10-9. Receive Error Causes
Note
User’s Manual U12768EJ4V1UD
START
SERIAL INTERFACE FUNCTION
D0
Cause
D1
D2
D6
D7
Parity
STOP
ASISn value
04H
02H
01H