upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 477

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Instruction Set List (2/4)
Arithmetic
operation
Saturated
operation
Logic
operation
Instruction
Note Only the lower halfword data is valid.
Group
ADD
ADD
ADDI
SUB
SUBR
MULH
MULH
MULHI
DIVH
CMP
CMP
SETF
SATADD
SATADD
SATSUB
SATSUBI
SATSUBR
TST
OR
ORI
AND
ANDI
Mnemonic
reg1, reg2
imm5, reg2 rrrrr010010iiiii
imm16,
reg1, reg2
reg1, reg2
reg1, reg2
reg1, reg2
imm5, reg2 rrrrr010111iiiii
imm16,
reg1, reg2
reg1, reg2
reg1, reg2
imm5, reg2 rrrrr010011iiiii
cccc, reg2
reg1, reg2
imm5, reg2 rrrrr010001iiiii
reg1, reg2
imm16,
reg1, reg2
reg1, reg2
reg1, reg2
reg1, reg2
imm16,
reg1, reg2
reg1, reg2
imm16,
reg1, reg2
Operand
APPENDIX C LIST OF INSTRUCTION SETS
rrrrr001110RRRRR
rrrrr110000RRRRR
iiiiiiiiiiiiiiii
rrrrr001101RRRRR
rrrrr001100RRRRR
rrrrr000111RRRRR
rrrrr110111RRRRR
iiiiiiiiiiiiiiii
rrrrr000010RRRRR
rrrrr001111RRRRR
rrrrr1111110cccc
0000000000000000
rrrrr000110RRRRR
rrrrr000101RRRRR
rrrrr110011RRRRR
iiiiiiiiiiiiiiii
rrrrr000100RRRRR
rrrrr001011RRRRR
rrrrr001000RRRRR
rrrrr110100RRRRR
iiiiiiiiiiiiiiii
rrrrr001010RRRRR
rrrrr110110RRRRR
iiiiiiiiiiiiiiii
Opcode
User’s Manual U12768EJ4V1UD
GR [reg2] ← GR [reg2] + GR [reg1]
GR [reg2] ← GR [reg2] + sign-extend
(imm5)
GR [reg2] ← GR [reg1] + sign-extend
(imm16)
GR [reg2] ← GR [reg2] − GR [reg1]
GR [reg2] ← GR [reg1] − GR [reg2]
GR [reg2] ← GR [reg2]
GR [reg2] ← GR [reg2]
(imm5)
GR [reg2] ← GR [reg1]
GR [reg2] ← GR [reg2] ÷ GR [reg1]
result ← GR [reg2] − GR [reg1]
result ← GR [reg2] − sign-extend (imm5)
if conditions are satisfied
GR [reg2] ← saturated (GR [reg2] + GR
[reg1])
GR [reg2] ← saturated (GR [reg2] + sign-
extend (imm5))
GR [reg2] ← saturated (GR [reg2] − GR
[reg1])
GR [reg2] ← saturated (GR [reg1] − sign-
extend (imm16))
GR [reg2] ← saturated (GR [reg1] − GR
[reg2])
result ← GR [reg2] AND GR [reg1]
GR [reg2] ← GR [reg2] OR GR [reg1]
GR [reg2] ← GR [reg1] OR zero-extend
(imm16)
GR [reg2] ← GR [reg2] AND GR [reg1]
GR [reg2] ← GR [reg1] AND zero-extend
(imm16)
then GR [reg2] ← 00000001H
else GR [reg2] ← 00000000H
Operation
Note
(Signed multiplication)
(Signed multiplication)
(Signed multiplication)
Note
Note
× GR [reg1]
× sign-extend
× imm16
(Signed division)
Note
Note
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