upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 129

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upd70f3017ay

Manufacturer Part Number
upd70f3017ay
Description
V850/sa1tm 32-/16-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet

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5.4.3 EP flag
exception occurs.
After reset: 00000020H
5.5 Exception Trap
V850/SA1, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap.
5.5.1 Illegal opcode definition
1111B.
Symbol
PSW
The EP flag in the PSW is a status flag used to indicate that exception processing is in progress. It is set when an
The exception trap is an interrupt that is requested when illegal execution of an instruction takes place. In the
• Illegal opcode exception: Occurs if the sub opcode field of the instruction to be executed next is not a valid
An illegal opcode is defined to be a 32-bit word with bits 5 to 10 being 111111B and bits 23 to 26 being 0011B to
31
EP
0
1
x: don’t care
15
x
x
Exception processing is not in progress
Exception processing is in progress
13
x
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
12
x
11
x
opcode.
10
1
1
0
1
1
1
Figure 5-13. Illegal Opcode
Figure 5-12. EP Flag (EP)
1
User’s Manual U12768EJ4V1UD
5
4
x
Exception Processing
x
x
x
0
x
31
x
8
x
NP EP ID SAT CY OV
x
7
x
27 26
6
x
0
1
5
0
1
to
1
1
4
23 22
1
1
3
x
21
x
2
20
x x x x x
S
1
17
0
Z
16
129

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