upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 240

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

240
Condition for clearing (ACKD = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL = 1
• When IICE changes from 1 to 0
• When RESET is input
Condition for clearing (STD = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock following
• Cleared by LREL = 1
• When IICE changes from 1 to 0
• When RESET is input
Condition for clearing (SPD = 0)
• At the rising edge of the address transfer byte’s first
• When IICE changes from 1 to 0
• When RESET is input
Remark
address transfer
clock following setting of this bit and detection of a start
condition
ACKD
STD
SPD
0
1
0
1
0
1
ACK was not detected.
ACK was detected.
Start condition was not detected.
Start condition was detected. This indicates that the address transfer period is in effect.
Stop condition was not detected.
Stop condition was detected. The master device’s communication is terminated and the bus is
released.
LREL: Bit 6 of IIC control register 0 (IICC0)
IICE:
Bit 7 of IIC control register 0 (IICC0)
CHAPTER 10
User’s Manual U12768EJ4V1UD
SERIAL INTERFACE FUNCTION
Detection of Start Condition
Detection of Stop Condition
Detection of ACK
Condition for setting (ACKD = 1)
• After the SDA line is set to low level at the rising
Condition for setting (STD = 1)
• When a start condition is detected
Condition for setting (SPD = 1)
• When a stop condition is detected
edge of the SCL’s ninth clock
(3/3)