upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 447

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Bus Timing (CLKOUT Asynchronous)
(T
Address setup time (to ASTB↓)
Address hold time (from ASTB↓)
Address float delay time from DSTB↓
Data input setup time from address
Data input setup time from DSTB↓
Delay time from ASTB↓ to DSTB↓
Data input hold time (from DSTB↑)
Address output time from DSTB↑
Delay time from DSTB↑ to ASTB↑
Delay time from DSTB↑ to ASTB↓
DSTB low-level width
ASTB high-level width
Data output time from DSTB↓
Data output setup time (to DSTB↑)
Data output hold time (from DSTB↑)
WAIT setup time (to address)
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
WAIT hold time (from ASTB↓)
HLDRQ high-level width
HLDAK low-level width
Bus output delay time from HLDAK↑
Delay time from HLDRQ↓ to HLDAK↓
Delay time from HLDRQ↑ to HLDAK↑
A
Remarks 1. T = 1/f
= –40 to +85°C, V
2. n: Number of wait clocks inserted in the bus cycle.
3. i: Number of idle states inserted after the read cycle (0 or 1).
4. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from
Parameter
The sampling timing changes when a programmable wait is inserted.
X1.
DD
CPU
= AV
(f
CPU
DD
: CPU operation clock frequency)
= BV
CHAPTER 17 ELECTRICAL SPECIFICATIONS
DD
t
t
t
t
t
t
= 2.7 to 3.6 V, V
t
t
t
t
t
t
SSTWT1
SSTWT2
HSTWT1
HSTWT2
t
DHQHA1
DHQHA2
t
t
t
t
t
t
t
t
t
t
SAWT1
SAWT2
HAWT1
HAWT2
t
t
DDST1
DDST2
t
WHQH
t
t
WSTH
DDOD
SODD
HDOD
WHAL
DHAC
SAST
HSTA
DSTD
SAID
SDID
HDID
DDA
WDL
FDA
Symbol
User’s Manual U12768EJ4V1UD
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<14>
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<18>
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<20>
<21>
<22>
<23>
<24>
<25>
<26>
<27>
<28>
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<40>
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
n ≥ 1
SS
= AV
Conditions
SS
= BV
SS
= 0 V, C
(1.5 + i)T – 15
(1 + n)T – 15
(1 + n)T – 20
(1 + i)T – 15
(0.5 + n)T
(1.5 + n)T
0.5T – 15
0.5T – 15
0.5T – 15
0.5T – 15
L
(1 + n)T
T – 15
T – 15
T + 10
T – 15
= 50 pF)
MIN.
0.5T
nT
0
0
(2n + 7.5)T + 25
(1.5 + n)T – 25
(2 + n)T – 25
(1 + n)T – 25
(1 + n)T – 25
1.5T – 25
1.5T + 25
T – 25
MAX.
15
2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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