upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 476

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

Instruction Set List (1/4)
476
Load/store
Arithmetic
operation
Instruction
Notes 1.
Group
2.
3.
SLD.B
SLD.H
SLD.W
LD.B
LD.H
LD.W
SST.B
SST.H
SST.W
ST.B
ST.H
ST.W
MOV
MOV
MOVHI
MOVEA
ddddddd is the higher 7 bits of disp8.
dddddd is the higher 6 bits of disp8.
ddddddddddddddd is the higher 15 bits of disp16.
Mnemonic
disp7 [ep],
disp8 [ep],
disp8 [ep],
disp16
[reg1], reg2
disp16
[reg1], reg2
disp16
[reg1], reg2
reg2,
disp7 [ep]
reg2,
disp8 [ep]
reg2,
disp8 [ep]
reg2,
disp16
[reg1]
reg2,
disp16
[reg1]
reg2,
disp16
[reg1]
reg1, reg2
imm5, reg2 rrrrr010000iiiii
imm16,
reg1, reg2
imm16,
reg1, reg2
reg2
reg2
reg2
Operand
APPENDIX C LIST OF INSTRUCTION SETS
rrrrr0110ddddddd
rrrrr1000ddddddd
rrrrr1010dddddd0
rrrrr111000RRRRR
dddddddddddddddd
rrrrr111001RRRRR
ddddddddddddddd0
rrrrr111001RRRRR
ddddddddddddddd1
rrrrr0111ddddddd
rrrrr1001ddddddd
rrrrr1010dddddd1
rrrrr111010RRRRR
dddddddddddddddd
rrrrr111011RRRRR
ddddddddddddddd0
rrrrr111011RRRRR
ddddddddddddddd1
rrrrr000000RRRRR
rrrrr110010RRRRR
iiiiiiiiiiiiiiii
rrrrr110001RRRRR
iiiiiiiiiiiiiiii
Opcode
User’s Manual U12768EJ4V1UD
Note 1
Note 2
Note 3
Note 3
Note 1
Note 2
Note 3
Note 3
adr ← ep + zero-extend (disp7)
GR [reg2] ← sign-extend (Load-memory
(adr, Byte))
adr ← ep + zero-extend (disp8)
GR [reg2] ← sign-extend (Load-memory
(adr, Halfword))
adr ← ep + zero-extend (disp8)
GR [reg2] ← Load-memory (adr, Word)
adr ← GR [reg1] + sign-extend (disp16)
GR [reg2] ← sign-extend (Load-memory
(adr, Byte))
adr ← GR [reg1] + sign-extend (disp16)
GR [reg2] ← sign-extend (Load-memory
(adr, Halfword))
adr ← GR [reg1] + sign-extend (disp16)
GR [reg2] ← Load-memory (adr, Word))
adr ← ep + zero-extend (disp7)
Store-memory (adr, GR [reg2], Byte)
adr ← ep + zero-extend (disp8)
Store-memory (adr, GR [reg2], Halfword)
adr ← ep + zero-extend (disp8)
Store-memory (adr, GR [reg2], Word)
adr ← GR [reg1] + sign-extend (disp16)
Store-memory (adr, GR [reg2], Byte)
adr ← GR [reg1] + sign-extend (disp16)
Store-memory (adr, GR [reg2], Halfword)
adr ← GR [reg1] + sign-extend (disp16)
Store-memory (adr, GR [reg2], Word)
GR [reg2] ← GR [reg1]
GR [reg2] ← sign-extend (imm5)
GR [reg2] ← GR [reg1] + (imm16 || 0
GR [reg2] ← GR [reg1] + sign-extend
(imm16)
Operation
16
)
CY OV S
Flag
Z SAT