upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 156

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

(2) Capture/compare registers 00, 10 (CR00, CR10)
156
Remark
Remark
ESn01
ESn11
CRn0 is a 16-bit register that functions as a capture register and as a compare register. Whether this register
functions as a capture or compare register is specified by using bit 0 (CRCn0) of the CRCn register.
(a) When using CRn0 as compare register
(b) When using CRn0 as capture register
CRn0 is set by using a 16-bit memory manipulation instruction.
These registers can be read/written when used as compare registers and can only be read when used as
capture registers.
RESET input sets this register to 0000H.
0
0
1
1
0
0
1
1
The value set to CRn0 is always compared with the count value of the TMn register. When the values of the
two match, an interrupt request (INTTMn0) is generated. When TMn is used as an interval timer, CRn0 can
also be used as a register that holds the interval time.
The valid edge of the TIn0 or TIn1 pin can be selected as a capture trigger. The valid edge of TIn0 or TIn1 is
set by using the PRMn register.
When the valid edge of the TIn0 pin is specified as the capture trigger, refer to Table 7-2. When the valid
edge of the TIn1 pin is specified as the capture trigger, refer to Table 7-3.
Caution In a mode in which the timer is cleared and started on a match between TMn and CRn0,
n = 0, 1
n = 0, 1
ESn00
ESn10
0
1
0
1
0
1
0
1
set the CRn0 register to other than 0000H. In the free-running mode or the TIn0 valid
edge clear mode, however, an interrupt request (INTTMn0) is generated after an overflow
(FFFFH) when CRn0 is set to 0000H.
Table 7-2. Valid Edge of TIn0 Pin and Capture Trigger of CRn0
Table 7-3. Valid Edge of TIn1 Pin and Capture Trigger of CRn0
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
CHAPTER 7 TIMER/COUNTER FUNCTION
Valid Edge of TIn0 Pin
Valid Edge of TIn1 Pin
User’s Manual U12768EJ4V1UD
Rising edge
Falling edge
Setting prohibited
No capture operation
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
CRn0 Capture Trigger
CRn0 Capture Trigger