upd70f3017ay Renesas Electronics Corporation., upd70f3017ay Datasheet - Page 489

• Manufacturer Part Number: upd70f3017ay
• Description: V850/sa1tm 32-/16-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

3rd
edition
Edition
Figure 9-5 Oscillation Stabilization Time Select Register (OSTS) Addition of oscillation
stabilization time when f
10.1 Overview Deletion and addition of products in Note
Figure 10-2 Serial Operation Mode Registers 0 to 2 (CSIM0 to CSIM2) Addition of
Notes
Figure 10-5 Settings of CSIMn (3-Wire Serial I/O Mode) Addition of Note
10.3 I
of products
Figure 10-7 Block Diagram of I
Table 10-2 Configuration of I
10.3.2 I
Figure 10-9 IIC Control Register 0 (IICC0) (3/4) Addition of condition of STT = 0 and
deletion of Note
Figure 10-9 IIC Control Register 0 (IICC0) (4/4) Addition of description and deletion of
Note 2
Figure 10-10 IIC Status Register 0 (IICS0) (2/3) Addition of Note
10.3.2 (3) IIC clock select register 0 (IICCL0) Addition of Remark
Figure 10-11 IIC Clock Select Register 0 (IICCL0) Addition of operation description of bit
3 (SMC) and bit 2 (DFC)
10.3.2 (4) IIC function expansion register 0 (IICX0) Addition
Table 10-3 Settings of Transfer Clock Addition of IIC communication frequency when f
= 20 MHz
10.3.4 (4) Acknowledge signal (ACK) Addition of description
10.3.5 I
10.3.6 (4) Wait cancellation method Addition of cancellation method
Table 10-7 Wait Periods Modification of wait period when SMC, CL1, CL0 = 010 and 110
Figure 10-27 Master Operation Flow Chart Correction
Table 10-8 Configuration of UARTn Addition of baud rate generator mode control
register 01 (BRGMC01)
10.4.2 UARTn control registers Addition of BRGMC01 register
10.4.2 (4) Baud rate generator mode control registers 0, 01 (BRGMC0, BRGMC01)
Addition of BRGMC01 register
Figure 10-35 Baud Rate Generator Mode Control Registers 0, 01 (BRGMC0,
BRGMC01) Addition of BRGMC01 register
10.4.4 (1) Register settings Addition of BRGMC01 register
10.4.4 (2) Generation of baud rate transmit/receive clock using main clock Correction
Table 10-9 Relationship Between Main Clock and Baud Rate Correction
Figure 11-2 A/D Converter Mode Register (ADM) Correction of conversion time
Figure 12-2 DMA Internal RAM Address Registers 0 to 2 (DRA0 to DRA2) Addition of
Caution
2
C Bus (
2
2
C control registers Addition of IIC function expansion register 0 (IICX0)
C interrupt request (INTIIC0) Addition of description
µ
PD703014AY, 703015AY, 703017AY, 70F3017AY) Deletion and addition
XX
= 10 MHz, f
Major Revision from Previous Edition
2
C Addition of IIC function expansion register 0 (IICX0)
2
C Correction
APPENDIX E REVISION HISTORY
XX
User’s Manual U12768EJ4V1UD
= 2 MHz
XX
CHAPTER 9
WATCHDOG
TIMER
CHAPTER 10
SERIAL
INTERFACE
FUNCTION
CHAPTER 11 A/D
CONVERTER
CHAPTER 12
DMA FUNCTIONS
Applied to:
(4/7)
489