MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 123

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.10.4 Reaction Time Calculation
MC68HC708AS48
MOTOROLA
NOTE:
—
Rev. 4.0
The actual acquisition and lock times can be calculated using the
equations in this subsection. These equations yield nominal values
under the following conditions:
The K factor in the equations is derived from internal PLL parameters.
K
K
8.4.2.2 Acquisition and Tracking
There is an inverse proportionality between the lock time and the
reference frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See
Manual and Automatic PLL Bandwidth
clock cycles, n
tracking mode entry tolerance,
Additionally, a certain number of clock cycles, n
ascertain that the PLL is within the lock mode entry tolerance,
Therefore, the acquisition time, t
and the acquisition to lock time, t
Refer to
ACQ
TRK
•
•
•
•
is the K factor when the PLL is configured in tracking mode. (See
is the K factor when the PLL is configured in acquisition mode, and
Correct selection of filter capacitor, C
Filter
Room temperature operation
Negligible external leakage on CGMXFC
Negligible noise
8.4.2 Phase-Locked Loop Circuit (PLL)
Clock Generator Module (CGM)
Capacitor.)
ACQ
, is required to ascertain that the PLL is within the
t
ACQ
t
AL
t
LOCK
=
=
ACQ
V
---------------- -
TRK
f
AL
V
---------------- -
=
RDV
f
DDA
RDV
DDA
, is an integer multiple of n
Modes.)
t
, before exiting acquisition mode.
, is an integer multiple of n
ACQ
----------------
K
-----------------
K
+
Acquisition/Lock Time Specifications
TRK
Modes.) A certain number of
ACQ
4
t
8
AL
F
(See
Clock Generator Module (CGM)
TRK
8.10.3 Choosing a
, is required to
for the value of f
Advance Information
8.4.2.3
TRK
ACQ
LOCK
/f
/f
RDV
RDV
RDV
.
123
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,
.