MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 364

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Byte Data Link Controller–Digital (BDLC–D)
Advance Information
364
DLOOP — Digital Loopback Mode Bit
RX4XE — Receive 4X Enable Bit
NBFS — Normalization Bit Format Select Bit
This bit determines the source to which the digital receive input
(BDRxD) is connected and can be used to isolate bus fault conditions
(see
this control bit allows the programmer to connect the digital transmit
output to the digital receive input. In this configuration, data sent from
the transmit buffer will be reflected back into the receive buffer. If no
faults exist in the BDLC, the fault is in the physical interface block or
elsewhere on the J1850 bus.
This bit determines if the BDLC operates at normal transmit and
receive speed (10.4 kbps) or receive only at 41.6 kbps. This feature
is useful for fast downloading of data into a J1850 node for diagnostic
or factory programming of the node.
This bit controls the format of the normalization bit (NB). (See
20-19.) SAE J1850 strongly encourages using an active long (logic 0)
for in-frame responses containing cyclical redundancy check (CRC)
and an active short (logic 1) for in-frame responses without CRC.
1 = When set, BDRxD is connected to BDTxD. The BDLC is now
0 = When cleared, BDTxD is not connected to BDRxD. The BDLC
1 = When set, the BDLC is put in 4X receive-only operation.
0 = When cleared, the BDLC transmits and receives at 10.4 kbps.
Byte Data Link Controller–Digital (BDLC–D)
Figure
in digital loopback mode.
is taken out of digital loopback mode and can now drive or
receive the J1850 bus normally (given ALOOP is not set). After
writing DLOOP to 0, the BDLC requires the bus to be idle for a
minimum of end-of-frame symbol (t
reception of a message. The BDLC requires the bus to be idle
for a minimum of inter-frame separator symbol (t
before allowing any message to be transmitted.
Reception of a BREAK symbol automatically clears this bit and
sets BDLC state vector register (BSVR $003E) to $001C.
20-14). If a fault condition has been detected on the bus,
tv4
MC68HC708AS48
) time before allowing a
tv6
) time
MOTOROLA
—
Figure
Rev. 4.0