MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 133

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MC68HC708AS48

Manufacturer Part Number
MC68HC708AS48
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
9.4.2.1 Power-On Reset
MC68HC708AS48
MOTOROLA
CGMXCLK
CGMOUT
PORRST
OSC1
RST
IAB
Rev. 4.0
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Another 64 CGMXCLK cycles later, the CPU
and memories are released from reset to allow the reset vector
sequence to occur.
At power-on, these events occur:
CYCLES
4096
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables CGMOUT.
Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow stabilization of the oscillator.
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.
Figure 9-7. POR Recovery
System Integration Module (SIM)
CYCLES
32
CYCLES
32
$FFFE
System Integration Module (SIM)
Reset and System Initialization
Advance Information
$FFFF
133

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