MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 351

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MC68HC708AS48
MOTOROLA
TRANSMITTER A
TRANSMITTER B
J1850 BUS
PASSIVE
PASSIVE
PASSIVE
ACTIVE
ACTIVE
ACTIVE
—
Rev. 4.0
Figure 20-12. J1850 VPW Bitwise Arbitrations
and arbitrate for the bus. If a CPU write to the BDR occurred after
104 • t
transmit, but will wait for the next IFS period to expire before attempting
to transmit the byte.
The variable pulse width modulation (VPW) symbols and J1850 bus
electrical characteristics are chosen carefully so that a logic 0 (active or
passive type) will always dominate over a logic 1 (active or passive type)
simultaneously transmitted. Hence, logic 0s are said to be dominant and
logic 1s are said to be recessive.
Whenever a node detects a dominant bit on BDRxD when it transmitted
a recessive bit, it loses arbitration and immediately stops transmitting.
This is known as bitwise arbitration.
Since a logic 0 dominates a logic 1, the message with the lowest value
will have the highest priority and will always win arbitration. For instance,
a message with priority 000 will win arbitration over a message with
priority 011.
This method of arbitration will work no matter how many bits of priority
encoding are contained in the message.
SOF
Byte Data Link Controller–Digital (BDLC–D)
BDLC
from the detection of the rising edge, then the BDLC will not
DATA
BIT 1
0
0
0
DATA
BIT 2
1
1
1
DATA
BIT 3
1
1
1
1
DATA
BIT 4
0
0
Byte Data Link Controller–Digital (BDLC–D)
DATA
BIT 5
0
0
TRANSMITTER A DETECTS
AN ACTIVE STATE ON
THE BUS AND STOPS
TRANSMITTING
TRANSMITTER B WINS
ARBITRATION AND
TRANSMITTING
CONTINUES
BDLC MUX Interface
Advance Information
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