MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 338

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Byte Data Link Controller–Digital (BDLC–D)
20.5.1 Rx Digital Filter
20.5.1.1 Operation
Advance Information
338
The receiver section of the BDLC includes a digital low pass filter to
remove narrow noise pulses from the incoming message. An outline of
the digital filter is shown in
The clock for the digital filter is provided by the MUX interface clock (see
f
signal, the current state of the receiver physical interface (BDRxD) signal
is sampled. The BDRxD signal state is used to determine whether the
counter should increment or decrement at the next negative edge of the
clock signal.
The counter will increment if the input data sample is high but decrement
if the input sample is low. Therefore, the counter will thus progress either
up toward 15 if, on average, the BDRxD signal remains high or progress
down toward 0 if, on average, the BDRxD signal remains low.
When the counter eventually reaches the value 15, the digital filter
decides that the condition of the BDRxD signal is at a stable logic level
1 and the data latch is set, causing the filtered Rx data signal to become
a logic level 1. Furthermore, the counter is prevented from overflowing
and can be decremented only from this state.
BDLC
INTERFACE
INTERFACE
PHYSICAL
RX DATA
(BDRxD)
CLOCK
FROM
MUX
Byte Data Link Controller–Digital (BDLC–D)
parameter in
Figure 20-5. BDLC Rx Digital Filter Block Diagram
D
INPUT
SYNC
Q
Table
UP/DOWN
20-3). At each positive edge of the clock
Figure
4-BIT UP/DOWN COUNTER
20-5.
OUT
MC68HC708AS48
D
LATCH
DATA
Q
RX DATA OUT
MOTOROLA
FILTERED
—
Rev. 4.0