MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 179

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MC68HC708AS48
MOTOROLA
Addr.
$001A
IRQ Status and Control Register
NOTE:
Register Name
—
Rev. 4.0
See page 183.
The external interrupt pin is falling-edge triggered and is software-
configurable to be both falling-edge and low-level triggered. The MODE
bit in the ISCR controls the triggering sensitivity of the IRQ/V
When an interrupt pin is edge-triggered only, the interrupt latch remains
set until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
interrupt latch remains set until both of the following occur:
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the ISCR masks all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the corresponding IMASK bit is clear.
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
(See
•
•
Figure 14-2. IRQ I/O Register Summary
(ISCR)
Figure
Vector fetch or software clear
Return of the interrupt pin to logic 1
Reset:
Read:
Write:
14-3.)
Bit 7
External Interrupt
R
R
0
0
= Reserved
6
R
0
0
5
R
0
0
4
R
0
0
IRQF
R
3
0
ACK
Functional Description
2
0
0
Advance Information
External Interrupt
IMASK
1
0
PP
pin.
MODE
Bit 0
0
179