MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 85

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

7.4.5 Condition Code Register
MC68HC708AS48
MOTOROLA
—
Rev. 4.0
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
V — Overflow Flag Bit
H — Half-Carry Flag Bit
I — Interrupt Mask Bit
Reset:
Read:
Write:
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an ADD or ADC operation. The
half-carry flag is required for binary coded decimal (BCD) arithmetic
operations. The DAA instruction uses the states of the H and C flags
to determine the appropriate correction factor.
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Overflow
0 = No overflow
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
1 = Interrupts disabled
0 = Interrupts enabled
X = Indeterminate
Bit 7
X
V
Central Processor Unit (CPU)
Figure 7-6. Condition Code Register (CCR)
6
1
1
5
1
1
H
X
4
3
1
I
Central Processor Unit (CPU)
N
X
2
Advance Information
X
1
Z
CPU Registers
Bit 0
C
X
85