MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 257
MC68HC708AS48
Manufacturer Part Number
MC68HC708AS48
Description
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FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC68HC708AS48.pdf
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17.4.10 Character Length
17.4.11 Character Reception
MC68HC708AS48
MOTOROLA
—
Rev. 4.0
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCC1) determines character length.
When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the
ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth
bit (bit 7).
During an SCI reception, the receive shift register shifts characters in
from the PTE1/RxD pin. The SCI data register (SCDR) is the read-only
buffer between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data
portion of the character transfers to the SCDR. The SCI receiver full bit,
SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the
received byte can be read. If the SCI receive interrupt enable bit, SCRIE
(SCC2), is also set, the SCRF bit generates a receiver CPU interrupt
request.
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
Functional Description
Advance Information
257
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