MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 310

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Serial Peripheral Interface (SPI)
18.14.1 SPI Control Register
Advance Information
310
Address:
The SPI control register:
SPRIE — SPI Receiver Interrupt Enable Bit
SPMSTR — SPI Master Bit
Reset:
Read:
Write:
•
•
•
•
•
•
This read/write bit enables CPU interrupt requests generated by the
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.
This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
1 = Master mode
0 = Slave mode
Enables SPI module interrupt requests
Selects CPU interrupt requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain
outputs
Enables the SPI module
SPRIE
$0010
Bit 7
R
0
Serial Peripheral Interface (SPI)
Figure 18-13. SPI Control Register (SPCR)
= Reserved
R
6
0
SPMSTR
5
1
CPOL
4
0
CPHA
3
1
MC68HC708AS48
SPWOM
2
0
SPE
1
0
MOTOROLA
—
Rev. 4.0
SPTIE
Bit 0
0